1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and in particular to semiconductor devices that incorporate strained silicon.
2. Related Technology
The continuous demand for improved performance in electronic devices has been addressed through advances in silicon processing and device technologies directed toward reduction in the size of individual semiconductor circuit components. However, economic and physical constraints are making continued reduction of device sizes more difficult, and so alternative solutions are being sought to allow increases in device performance to continue.
One option for increasing the performance of MOSFETs is to enhance the carrier mobility of the MOSFET semiconductor material so as to reduce resistance and power consumption and to increase drive current, frequency response and operating speed. A method of enhancing carrier mobility that has become a focus of recent attention is the use of silicon material to which a tensile strain is applied. “Strained” silicon may be formed by growing a layer of silicon on a silicon germanium substrate. The silicon germanium lattice is more widely spaced on average than a pure silicon lattice because of the presence of the larger germanium atoms in the lattice. Since the atoms of the silicon lattice align with the more widely spaced silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. The amount of tensile strain applied to the silicon lattice increases with the proportion of germanium in the silicon germanium lattice.
The tensile strain applied to the silicon lattice increases carrier mobility. Relaxed silicon has six equal valence bands. The application of tensile strain to the silicon lattice causes four of the valence bands to increase in energy and two of the valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus the lower energy bands offer less resistance to electron flow. In addition, electrons encounter less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon as compared to relaxed silicon, offering a potential increase in mobility of 80% or more for electrons and 20% or more for holes. The increase in mobility has been found to persist for current fields of up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance.
An example of a MOSFET using a strained silicon layer is shown in FIG. 1. The MOSFET is fabricated on a substrate comprising a silicon germanium layer 10 on which is grown an epitaxial layer of strained silicon 12. The MOSFET uses conventional MOSFET structures including deep source and drain regions 14, shallow source and drain extensions 16, a gate oxide layer 18, a gate 20 surrounded by spacers 22, 24, silicide source and drain contacts 26, a silicide gate contact 28, and shallow trench isolations 30. The channel region of the MOSFET includes the strained silicon material, which provides enhanced carrier mobility between the source and drain.
While the incorporation of strained silicon in MOSFETs enhances some aspects of MOSFET performance, other aspects of MOSFET performance are degraded. One source of performance degradation is a decrease in the threshold voltage Vt under then gate at the edges of the active area, which results in an enhanced leakage current at the ends of the gate. The mechanism that produces this effect is explained with reference to FIGS. 2a-2d. FIG. 2a shows a generalized plan view of the strained silicon MOSFET of FIG. 1. In this view it is seen that the shallow trench isolations 30 surround an active area in which are formed a source region 32 and drain region 34. The gate structure 36 bisects the active area between the source region 32 and the drain region 34. FIG. 2b shows a cross section of the MOSFET of FIG. 2a taken along line A-A′. As shown in FIG. 2b, the gate structure 36 and the strained silicon layer 12 span the distance between the shallow trench isolations 30.
The view of FIG. 2b is idealized, in that the shallow trench isolations 30 are shown as having essentially linearly tapered sidewall profiles. However, in actual implementations such linearity is difficult to achieve using conventional processing. The difficulty arises from the differences in the etch rates of silicon and silicon germanium. Typically a single etch chemistry such as HBr/Cl2He/O2 is used to etch both the strained silicon and the silicon germanium. However, this chemistry etches the material of the strained silicon layer 12 at a slower rate than the material of the silicon germanium layer 10. As a result, significant undercutting of the silicon germanium 10 occurs. As shown in FIG. 2c, this undercutting creates a strained silicon overhang portion 38. The strained silicon overhang portion 38 is sandwiched between the gate insulator 18 and the insulating material of the shallow trench isolation 30. FIG. 2d shows a cross section of the structure of FIG. 2c taken along line B-B′. As shown in FIG. 2d, the overhang portion 38 of the strained silicon layer effectively forms the channel region of a silicon on insulator (SOI) structure that is comprised of the gate 20, the gate insulator 18, and an SOI substrate consisting of the portion of the shallow trench isolation 30 that underlies the strained silicon overhang portion 38. Because the strained silicon layer is thin, typically 200 Angstroms or less, the depletion region 40 between the source and drain regions of the MOSFET extends through the entire thickness of the strained silicon overhang portion 38, resulting in a fully depleted silicon on insulator structure beneath each end of the gate. This is highly undesirable since the threshold voltage Vt in the region of the fully depleted SOI structure is significantly lower than the threshold voltage in the remainder of the MOSFET, resulting in unacceptable leakage current at the ends of the gate.
Therefore, strained silicon MOSFETs fabricated in accordance with conventional technology gain the benefit of enhanced carrier mobility but are degraded by greater leakage current in the regions under the ends of the gate.